package CPU.rv64_1stage

import CPU.common._
import chisel3._

class CoreIo(implicit val conf: SodorConfiguration) extends Bundle
{
  val imem = new MemPortIo(conf.xprlen)
  val dmem = new MemPortIo(conf.xprlen)
//  val ddpath = Flipped(new DebugDPath())
//  val dcpath = Flipped(new DebugCPath())
  val reset = Input(Bool())
}

class Core(implicit val conf: SodorConfiguration) extends Module
{
  val io = IO(new CoreIo())
  io := DontCare
  val c  = Module(new CtlPath())
  val d  = Module(new DatPath())
  c.io.ctl  <> d.io.ctl
  c.io.dat  <> d.io.dat

  io.imem <> c.io.imem
  io.imem <> d.io.imem

  io.dmem <> c.io.dmem
  io.dmem <> d.io.dmem
  io.dmem.req.valid := c.io.dmem.req.valid
  io.dmem.req.bits.typ := c.io.dmem.req.bits.typ
  io.dmem.req.bits.fcn := c.io.dmem.req.bits.fcn
}

object u_core {
  implicit val sodor_conf = SodorConfiguration()
  def main(args: Array[String]): Unit = {
    chisel3.Driver.execute(args, () => new Core())
  }
}

